Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, and retaining its stored data even after power is turned off. In spite of the higher cost compared to magnetic disk storage, flash memory is increasingly being used in mass storage applications. Conventional mass storage, based on rotating magnetic medium such as hard drives and floppy disks, is unsuitable for the mobile and handheld environment. This is because disk drives tend to be bulky, are prone to mechanical failure and have high latency and high power requirements. These undesirable attributes make disk-based storage impractical in most mobile and portable applications. On the other hand, flash memory, both embedded and in the form of a removable card are ideally suited in the mobile and handheld environment because of its small size, low power consumption, high speed and high reliability features.
The memory devices typically comprise one or more memory chips that may be mounted on a card. Each memory chip comprises an array of memory cells supported by peripheral circuits such as decoders and erase, write and read circuits. The more sophisticated memory devices also come with a controller that performs intelligent and higher level memory operations and interfacing. There are many commercially successful non-volatile solid-state memory devices being used today. These memory devices may employ different types of memory cells, each type having one or more charge storage element. Examples of EEPROMs and methods of manufacturing them are given in U.S. Pat. No. 5,595,924. Examples of flash EEPROMs, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, 5,661,053, 5,313,421 and 6,222,762. Examples of memory devices with NAND cell structures are described in U.S. Pat. Nos. 5,570,315, 5,903,495, and 6,046,935. Examples of memory devices with a dielectric layer for storing charge have been described by Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp. 543-545, and in U.S. Pat. Nos. 5,768,192 and 6,011,725.
A memory device is usually organized as a two-dimensional array of memory cells arranged in rows and columns and addressable by word lines and bit lines. The array can be formed according to an NOR type or an NAND type architecture. Examples of NOR type memories are disclosed in U.S. Pat. Nos. 5,172,338 and 5,418,752. Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Pat. Nos. 5,570,315, 5,774,397 and 6,046,935.
A memory will often have defective portions, either from the manufacturing process or that arising during the operation of the device. In particular, in order to maximize manufacturing yield, defects found upon manufacturing are corrected to salvage an otherwise defective product. A number of techniques exists for managing these defects including error correction coding or remapping portions of the memory, such as described in U.S. Pat. Nos. 5,602,987, 5,315,541, 5,200,959, 5,428,621, and US 2005/0141387 A1. The discloures of these publications are hereby incorporated herein by reference.
After manufacturing, a memory chip is tested prior to shipment. If a defect is found, the chip may be salvageable by substituting the defective portion of the memory with a redundant portion. A common type of defect found in memory is due to problems in a column of the array. For example, in a flash memory a column defect may be due to any one of the following errors in the memory cell area: bit line to bit line shorts; bit line shorted to other signals; bit line opens; bad cells that do not program or are too slow to program; and/or bad data latches.
Conventional column redundancy scheme replaces the whole column, including the bit lines, sense amplifiers, and data latches within in the column. The redundancy scheme also has is a high speed match circuit along with separate access signals which get enabled when a bad column is encountered.
One prior art system managing defective columns on the memory chip itself uses a binary decoding scheme to manage bad column replacement. The address from the host is first latched into a register and the column address is incremented by a 10-bit adder to manage the columns from 0 to 540 bytes. The column address (10 bits) is then pre-decoded into 15 to 20 lines which run through the column decoder area. Three signals are chosen from among these 15 to 20 lines to form a column select. Bad columns in this binary decoding system are managed by comparing an incoming column address with a list of bad column addresses. If a match is found, the incoming column address is reassigned to another, good column address. If the incoming address does not match the bad column addresses, the incoming column address is not changed. The binary column select scheme has a high degree of flexibility in locating random column addresses. However, it has the disadvantage is that it is relatively slow because of the multiple stages of logic necessary to replace a defective column, and this makes it difficult for the binary decoding scheme to run much faster than a 20 MHz data input or output rate.
Also, in the case of a memory array with an architecture serviced by sets of sense amplifiers from both top and bottom of the array, defective columns may not be efficiently remapped due to the location of a redundant column relative to each set of sense amplifiers.
Therefore there is a general need for high performance and high capacity non-volatile memory with improved performance. In particular, there is a need for defect management with improved performance and efficiency.